Low TRL research in micro-electronics and integration technologies for industrial solutions (RIA)

Topic description

ExpectedOutcome:

Projects are expected to contribute to the following outcomes:

• Innovative semiconductor and micro-nanoelectronic systems design concepts supporting very low energy consumption, integrated security, connectivity, sensing, actuating and embedded functions suited to mixed analogue/RF and digital circuits.
• Alternative^[1] semiconductor manufacturing process technologies able to sustain in the mid- and long-terms the fast pace evolution of device performance, miniaturisation and cost, while reducing environmental footprint.
• Very advanced packaging solutions aiming at extreme miniaturisation and integration of multiple functions such as communication (RF, mmW or THz), sensing, actuating, power management and active/passive integration

Proposals should:

• Address low-TRL research with high potential not yet demonstrated in the design, fabrication process and/or packaging segments of the micro-nano-electronics and integration technologies value chain.
• Innovation focus can be on materials, physic concepts, device architecture or integration technologies.
• Provide a projection of the expected gains and main figures of merit of the proposed approaches.

Multi-disciplinary research activities should be address along part of the value chain from materials, processes, equipment, metrology, back-end processing to packaging, integration and tests.

International cooperation is encouraged, especially with leading semiconductor countries (e.g. Japan, South Korea, Taiwan) in support of EU policies (and outcome of the CSA on Int’ cooperation in SC).

In this topic the integration of the gender dimension (sex and gender analysis) in research and innovation content is not a mandatory requirement.

Activities are expected to start at TRL 1-2 and achieve TRL 3-4 by the end of the project – see General Annex B.

[1]Alternative to mainstream Silicon CMOS technologies